As integrated circuit features and Critical Dimensions (CD's) get continually smaller, more and more stringent requirements are made on the lithographic processes for defining the patterns. Historically the resolution limits for, and therefore the limits for the utility of, optical lithography, have been pushed smaller and smaller with time, as is illustrated in FIG. 1. This has necessitated the use of smaller optical exposure wavelengths. Currently available manufacturing lithography solutions are based on 193 nm dry or immersion/wet lithography (using ArF lasers for exposure), with the resolution limit being at about a 65-70 nm pitch. As CD's and pitches become even smaller other methods are proposed to overcome the printability issues.
Double patterning has been proposed to overcome these issues, using several solutions and integration schemes. US Patent Publication 20070148968 describes some of these schemes, as do the following publications:    1. Maaike Op de Beeck et al; Manufacturability Issues with Double Patterning for 50 nm Half Pitch Single Damascene ‘Applications, Using RELACS Shrink and Corresponding OPC; Optical Microlithodgraphy XX, Proc SPIE Vol 6520, 2007;    2. Mircia Dusa et al; Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets; Optical Microlithography XX, Proc SPIE Vol 6520, 2007;    3. Byungjoon Hwang et al; Smallest Bit-Line Contact of 76 nm Pitch on NAND Flash Cell by Using Reversal PR (Photo Resist) and SADP Double Patterning) Process; Proc 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conf; pp 356 ff;    4. Seo-Min Kim et al; Issues and Challenges of Double Patterning Lithography in DRAM; Optical Microlithodgraphy XX, Proc SPIE Vol 6520, 2007.
As seen in the above references, there are two main approaches in the art to double patterning. The first approach involves dual exposure, with a double or a single etch. In this case, the CD's and spaces depend on the precision of both exposures and their mutual alignment. The second approach, Self-Aligned Double Patterning (SADP), requires only one exposure under critical conditions, with a complementary pattern being created in a non-lithographical way. The Self-Aligned Double Patterning can be accomplished by a Positive Tone method or a Negative Tone method
A first solution, illustrated in FIG. 2, is double exposure—it can be executed with a single or double etch. In an exemplary implementation, in order to transfer a pattern to a substrate 205, a hard mask 210 and a resist 215 are used for patterning. A first patterning step and etch step yield a set of patterns 220 in the resist and hardmask. The second patterning step is used to generate patterns 225 in a resist in addition to the patterns already transferred to hardmask. The second pattern features, together with the first patterning features create the pattern with dimensions not achievable with single exposure. The final pattern 230 on the substrate is achieved by etching the target material using a mask, which combines the first pattern pre-etched in hardmask layer and the second pattern of resist.
A second solution is known as self-aligned double patterning with spacers. This solution utilizes spacers and sacrificial layers to create a complementary line pattern aligned to the original line pattern. Two different methods of self-aligned double patterning are known as positive tone and negative tone patterning. Positive tone patterning is illustrated in FIG. 3a. Target layer 300 is covered by a sacrificial template layer 305. resist layer 310 exposure and development is used to yield features 315 with a pitch twice the target pitch, and required linewidth. The pattern is etched off in the sacrificial template layer, and the resist is removed. Sidewall spacers 325 of width equal to the desired width of the target lines are then formed, adjacent to the pattern lines, using a standard methods of conformal deposition of a film followed by an isotropic dry etch. The spacer processing exposes the tops of the sacrificial template layer which then is selectively removed, leaving behind the sidewall spacers. The spacers, which have a desired pitch of the target pattern, are used as masks during the etching of final pattern in target layer, and then stripped.
Negative tone patterning is illustrated in FIG. 3b. The flow is similar to positive tone patterning up through the formation of the sidewall spacers 325, which for this particular flow are sacrificial spacers. At this point, another sacrificial layer 330 is deposited as a gap fill, and then planarized down to the top of the spacers, to create a pattern which is complementary to the spacer pattern. At this point the sacrificial spacers are removed, leaving remaining pattern features 335, with a pitch equal to the target pitch. Those features are used as a mask during etching of the final pattern into the target layer. FIGS. 3a and 3b are from Bencher, C., SADP: The Best Option; Nanochip Tech. Journal, issue 2007, pg. 8.
Patterns generated by double patterning may have more variability issues than those from single patterning. Each sub-pattern, i.e., the portion of the pattern produced by a different portion of the double patterning process, (e.g., the gap fill features vs. the line features in the negative tone patterning) has its own CD control issues, and additionally problems can result arising from the mutual alignment of the sub-patterns. In general, for the purposes of this disclosure, a sub-pattern will refer to a portion of the pattern which is produced by the same process steps and which is affected in the same way, e.g. in terms of feature dimensions and alignment, by process or other variations. These CD and alignment issues are manifested differently for the three types of double patterning outlined above and can affect the individual linewidths, the line-to-line spacing, and alignment error. FIG. 4 illustrates a pattern generated by a double patterning process. Features A and B shown in cross section represent features resulting from differing steps in the double patterning processes, and the spaces may also be non-symmetric, depending on how the spaces are oriented to features A and B. Table 1 below summarizes the sources of variability, and their impact on line CD's, line spacing, and line-to-line alignment for the three types of double patterning.
TABLE 1Potential Line Width and Space Variation in Double PatterningSelf-AlignedDoubleSelf-Aligned DoubleDouble Pattern withPatter-Double Exposure (twoPattern with SpacerSpacerninglitho steps with(Positive Tone:(Negative Tone:schemepattern alignment)Lines)Spaces)SourcesLine1Line2Line1-Line2Line1 CDSpacerLine 1 CDSpacerof vari-CDCDAlignmentthicknessthicknessabilityImpactDirectDirectNoneNoneDirect - sameDirect -No impacton Lineononimpact onwider Line1on Line1CDLine1Line2both lineswill alsoCD, changecausein Line2 CDsmallerLine2 CDImpactBothBothSpacesDirect, butOnly oneNoneDirect -on Linespacesspaceschange, butsum ofspace widthboth spacesSpacingchangechangesum ofneighboris modulatedwith changesimilarsimilarneighborspacesby spacerthe samespacesremainsthicknessway asremainssamespacersamewidthImpactNoneNoneDirectDirect, errorSpacerNoneNoneon Line-in definingthicknessLinethe first(sets LineAlign-space willCD) willmentcause aimpact onlymismatchone space,betweenandspaces andmismatchwill be seenbetweenas alignmentspaces willerrorbe seen asalignmenterrorNote that in Table 1, CD and alignment errors are treated separately, but they may occur simultaneously, further complicating the resulting Line/Space variation.
To monitor and control the double patterning processes, measurements need to be made of lines, spaces, CD's, and line-to-line alignment. The standard method for doing this involves SEM-based CD measurements for lines and spaces. This method is time consuming, and it can be done only with an exposed pattern. CD-SEM's are well suited to doing in-line, real-time process characterization so as to make mid-course corrections, but the amount of data collected is limited not only due to the actual time and costs of doing the CD-SEM's, but also due to the associated costs of delaying processing. As a result, detailed in-line characterization of many points usually does not happen using CD-SEM analysis. And CD-SEM measurement after completing the processing necessitates destructive and costly failure analysis An electrical test vehicle and method which could provide CD, linewidth, space width, and alignment data to characterize the double patterning processes would be preferable for its capability to obtain large amounts of data collection after processing. Furthermore, electrical tests would also provide information about process variability and/or possible mis-processing. Such electrical tests would be very well suited for building the database and providing a feedback loop process for performance and yield of manufactured products.